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GENNUM
CORPORATION
Programmable Analog Signal Processor
GP520A - DATA SHEET
FEATURES * programmable parameters
- gain - low pass filter - high pass filter - AGC threshold - release time - MPO - receiver bias voltage
Principle features of the preamp are the input impedance 100 k and a gain of 14 dB. The programmable filter block is composed of a low pass and high pass filter which generates a range of high and low pass corner frequencies. Although the control current to this block varies linearly, linear to logarithmic conversion is performed internally in order to adjust the corner frequencies logarithmically. Both filters feature a 12 dB/octave rolloff and unity gain. The filters are followed by an AGC block. Up to 35 dB of adjustable gain is provided as well as programmable threshold and release time. The attack time of the AGC block remains fixed and is independent of the release time. The output current is driven into the preamp of the clipper, thus, the AGC converts a voltage input into a current output and is therefore, a transconductance block. The next stage is an electronic MPO control peak "clipper" providing electronic clipping of the signal and setting of the maximum output level. The clipper output is also a transconductance block and drives a 40 k resistor (ROUT 8) tied to the supply. The input of the final stage is an inverting operational amplifier. A feedback resistance of 240 k is provided internally and this final stage is thus configured as a voltage drive output stage. The DC bias current through the receiver is also programmable.
* on-chip voltage regulator * typical gain 60 dB * voltage drive output stage * telecoil preamp STANDARD PACKAGING * Chip (136 x 110 mils) Au Bump CIRCUIT DESCRIPTION The GP520A is a programmable analog signal path IC designed for use in hearing instruments. The GP520A's programmable parameters are adjusted by external programming currents, such as generated by the GP521. The GP520A provides a 2.5 A reference current for use by the GP521. Sixteen settings are possible in the GP521, allowing the Programmable Current Sink (PCS) to sink between 0 and 1.875 x IREF . The GP520A is composed of five functional blocks. The input preamp, a filter block, the AGC block, MPO clipper and the output stage.
V CC V REG 9 13
VOLTAGE REGULATOR
A OUT 15
HPFB 18
HP 19
LPFB 22
BUFFER IN 24
BUFFER OUT 26
RECT. IN 27
FULL WAVE RECTIFIER
CAGC 1
AVERAGING CIRCUIT THRESHOLD
DELTA CCOMP OUT B IN 3 5 31
B OUT CCLIP 7 30
V cc
R +
LP FILTER
R OUT 8
AGC VC AMP CLIPPER
28 50k 29 A IN 14 R +
PREAMP
COUT 8
+ HP 2R
FILTER
RIN14
40K
-
10
RF
DIN
R 10K
LIN/LOG CONVERTER
OUTPUT
+
LIN/LOG CONVERTER LIN/LOG CONVERTER
11
DOUT
I REF 16 I REF 25 I REL
VBIAS 23 I GAIN 4 I CLIP 17 I BIAS
12 P GND
6 GND
20 I HP
21 I LP
2 I THRESH
All resistors in ohms, all capacitors in farads unless otherwise stated.
FUNCTIONAL BLOCK DIAGRAM
Revision Date: May 1998 Document No. 510 - 78 - 06
GENNUM CORPORATION P.O. Box 489, Stn. A, Burlington, Ontario, Canada L7R 3Y3 tel. +1 (905) 632-2996 Web Site: www.gennum.com E-mail: hipinfo@gennum.com
CHIP PAD DIAGRAM ABSOLUTE MAXIMUM RATINGS
PARAMETER Supply Voltage Pad 3, 8, 10, 11, 13, 17 Pad 1, 15, 16, 18, 19, 22, 24, 26 Pad 4, 5, 7, 14, 20, 21, 23, 25, 27 Pad 2 VALUE / UNITS 5V -0.1 V to VCC + 0.1 V -0.1 V to VREG + 0.1 V -0.1 V to 0.7 V
6 31 30 29 28 27
CCOMP
1 2 3 4 5
CCLIP
TEL-B TEL-C RECT.IN
BUFFER OUT 26
CAGC I THRESH
DELTA OUT
I REL 25
BUFFER IN 24
I CLIP B IN GND B OUT COUT V CC
I GAIN 23 LPFB 22 I LP 21 I HP 20
VREG -0.7 V to VREG + 0.1 V CAUTION CLASS 1 ESD SENSITIVITY
7 8 9
GP520A
HP 19 HPFB 18 I BIAS 17 I REF 16 A OUT 15
A IN 14
10 DIN 11 DOUT
ELECTRICAL CHARACTERISTICS
12
PGND 13 V REG
All parameters are measured at TA = 25oC All gains are calculated from equation G = 20 LOG (OUT/IN) where OUT and IN are appropriate voltage or current increases. All resistances are calculated according to equation R = (V P - VQ) / ICOND where V P is voltage on the pad loaded with I COND current. V Q - quiescent (unbias) voltage measured on the pad, (nothing connected to the pin). V P is the actual voltage measured on the pad at given condition (where P is pad number). For all graphs IREF is measured with 0.5V biased voltage on pin 16.
GENERAL PARAMETER Amplifier Current Minimum Voltage REGULATOR TESTS Regulator Voltage (Pad 13) Short Circuit Current (Pad 13) CURRENT REFERENCE Current Reference (Pad 16) PREAMPLIFIER Quiescent Voltage on Pad 14 Quiescent Voltage on Pad 15 Input Resistance (Pad 14) Output Swing High (Pad 15) Output Swing Low (Pad 15) VQ14 VQ15 RIN 14 VOH VOL ISOURCE I14 = 0.3A (S2 closed)(Note 1) V 14 = 0.8V (S3 closed)(Note 1) V1
=
SYMBOL IAMP VCC
CONDITIONS All PCS set to 15
MIN 1.1
TYP 600 -
MAX -
UNITS A V
VREG ISC S1 -- closed
-
0.98 2.0
-
V mA
IR
-
2.5
-
A
600 600 200 -200
100 -
-
mV mV k mV mV A A
0.4V (S3 closed)
Max Source Current (Pad 15)
V14 = 0.8V (S3, S4 closed) V15 = VQ15+100mV V14 = 0.4V (S3,S4 closed) V15 = VQ15-100mV V14= V Q14 10mV (S3 closed)
30
-
-
Max Sinking Current (Pad 15)
ISINK
30
-
-
Preamp Voltage Gain
NOTE: 1. VOL = VOH = V P15 - VQ15 510 - 78 - 06
GAIN
-
14
-
dB
All switches remain OPEN unless otherwise stated in CONDITIONS column.
2
S4 1.3V V CC V REG S1 33 A IN 14 + 40K
68n V15
68n
10n 10n 10K B OUT 30 5 7 B OUT VCC 2k2 11 DOUT
+ 9 A OUT
+
CAGC 15 26 27 1 31
13
VOLTAGE REGULATOR
PREAMP
S2
S3
RIN14
I14
10K V14 + 12 P GND 6 GND
All resistors in ohms, all capacitors in farads unless otherwise stated.
Fig. 1 Preamplifier and Regulator Test Circuit HIGH PASS FILTER PARAMETER Quiescent Voltage on Pad 18 Quiescent Voltage on Pad 19 Quiescent Voltage on Pad 20 Maximum DC Current from Pad 19 Minimum DC Current from Pad 19 Buffer Gain Input Resistance Pad 20 SYMBOL VQ18 VQ19 VQ20 IHP MAX IHP MIN GAIN RIN20 I HP = 0A ( S3 closed) IHP=1.875 x I R (S3 closed) V19 = VQ19 100mV
(S2 closed)
CONDITIONS
MIN -
TYP 650 650 550 2 200
MAX -
UNITS mV mV mV A nA
-
0 13
-
dB k
IHP = I R
All switches remain OPEN unless otherwise stated in CONDITIONS column.
+V19 S2 V CC 9 V
REG
68n S3 LPFB
68n
10n 10n 10K B B OUT 7 2k2 11 DOUT
HPFB HP 18 19
CAGC 26 27 1 30
IN
VCC
22
31 5
13 R
33
2R FILTER
+ HP -
R
LIN/LOG CONVERTER 12 P GND 6 GND I HP 20 I HP
RIN
0.6 V
LIN/LOG CONVERTER 21 I LP
All resistors in ohms, all capacitors in farads unless otherwise stated.
Fig. 2 High Pass Filter DC Test Circuit 3
510 - 78 - 06
LOW PASS FILTER
PARAMETER Quiescent Voltage on Pad 21 Quiescent Voltage on Pad 22 Quiescent Voltage on Pad 24 Quiescent Voltage on Pad 26 Maximum DC Current from Pad 22 Minimum DC Current from Pad 22 Output Swing High (Pad 26) Output Swing Low (Pad 26) Max Sinking Current from Pad 26 SYMBOL VQ21 VQ22 VQ24 VQ26 ILP MAX ILP MIN VOH VOL ISINK ILP = 0A (S1 closed) ILP =1.875 x I R (S1 closed) V24 = VQ24 + 100mV (S2 closed)(Note 1) V24 = VQ24 - 100mV (S2 closed )(Note 1) V24 = 0.4V; V 26 = VQ26 - 100mV CONDITIONS MIN 30 TYP 550 650 650 650 2.0 0.7 100 -100 MAX UNITS mV mV mV mV A A mV mV A
(S2, S3 closed) Max Sourcing Current to Pad 26 ISOURCE V24 = 0.8V; V 26 = VQ26 100mV (S2, S3 closed) Buffer Gain Input Resistance (Pad 21)
NOTE: 1. VOH = V OL = V P26 - V Q26
-30
-
-
A
GAIN RIN21
V26 = VQ26 100mV ILP = I R
-
0 13
-
dB k
All switches remain OPEN unless otherwise stated in CONDITIONS column.
+
+1.3 V S1 V CC 9 V REG 33 13 R LPFB BUFFER IN 22
V24 S2
+
S3
V26 68n 68n 10n 10n 10K B 31 B VCC
BUFFER OUT 24 26
RECT. C AGC IN 27 1 30
IN
OUT
5
7 2k2
+ LP R
FILTER
11 DOUT
0.6 V R IN 12 P GND 6 GND
LIN/LOG CONVERTER
I REF
21 I LP
16 I REF
All resistors in ohms, all capacitors in farads, unless otherwise stated.
I LP
Fig. 3 Low Pass Filter DC Test Circuit
510 - 78 - 06
4
1n5 680p 2n2 V CC 9 13 33 R +
PREAMP VOLTAGE REGULATOR
TP 10n 10n 10K BOUT 1 31 30 5 BIN 7 VCC
2n2 HPFB 18 HP 19
68n BUFFER LPFB OUT 24 BUFFER 26 27 22 IN R + LP FILTER
68n
A OUT 15
2k2 11 DOUT
AIN 14 10 RIN14
2R
+ HP
FILTER
40K
-
R 10K
0.6V 12 6 P GND GND
LIN/LOG CONVERTER
0.6 V
LIN/LOG CONVERTER
20 I HP
21 I LP
All resistors in ohms, all capacitors in farads, unless otherwise stated.
PINK NOISE GENERATOR I HP I LP
Fig. 4 AC Test Circuit for High & Low Pass Filters
10k
10k
1k
CORNER FREQUENCY (HZ)
CORNER FREQUENCY (Hz)
IHP = 1.875 x IR
1k 100 80
0
0.25
0.5
0.75
1
1.25
1.5
1.75
2
700
0
0.25
0.5
0.75
1
1.25
1.5
1.75
2
NORMALIZED I HP / I R CURRENT
NORMALIZED I HP / I R CURRENT
Fig. 5 High Pass Filter Corner Frequency vs IHP Current (Note 1) (Fig.4 Test Circuit)
Fig. 6 Low Pass Filter Corner Frequency vs I LP Current (Note 1) (Fig.4 Test Circuit)
NOTES: 1. Corner frequency calculated in reference to signal at 3 kHz
5
510 - 78 - 06
AGC CONTROL STAGE
PARAMETER Quiescent Voltage on Pad 2 Quiescent Voltage on Pad 3 Quiescent Voltage on Pad 23 Quiescent Voltage on Pad 25 Quiescent Voltage on Pad 27 Release Current Max (Pad 1) Release Current Min (Pad 1) Input Resistance (Pad 25) Input Resistance (Pad 27) SYMBOL VQ2 VQ3 VQ23 VQ25 VQ27 IREL MAX IREL MIN RIN25 RIN27 IREL = 0 (S1 closed) IREL = 1.875 x I R (S1 closed) IREL = I R I27 = IR IGAIN =I R x 2 x 1.875 VP26=30 mVpp ITHRESH =1.875 x I R (Note 1) ITHRESH =1.875 x I R (Note 2) V26 = 25 mVpp ITHRESH =I R, I GAIN = 2 x 1.875 x I R V26 = 100 mVpp (Note 3) Limiting Level Range LIMRANGE CMPRAT IGAIN = I R x 2 x1.875 (Note 4) V26 = 100 mVpp ITHRESH =I R IGAIN = 2 x 1.875 x I R (Note 5) 13 dB CONDITIONS ITHRESH = I R IGAIN = IR x 1.875 MIN TYP 400 700 500 500 600 300 30 17 4 160 MAX UNITS mV mV mV mV mV nA nA k k A/V
Max Transconductance (Pad 26 to VO ) G MAX
Gain Range (Pad 26 to V ) o Output Limiting Level (Pad 3)
GAIN RANGE OUTLIM
-
33
-
dB ARMS
-
0.7
-
AGC Compression Ratio
-
5
-
Unless otherwise stated in CONDITIONS column all switches remain OPEN, all current sources are 0A NOTES: 1. G MAX = V o / (V 26 x 1M)
4. LIM
RANGE
= 20 LOG (Vo [I THRESH=1.875 x I R]/Vo [I THRESH =0] )
2. GAINRANGE = 20 LOG ( V o[I GAIN = 2 x1.875 x I R]/ V o [I GAIN = 0]) 3. OUT LIM = V / 1M
o
5. CMP
RAT
=
10 20 LOG (V o [V 26=5.62mVRMS]/V o[V 26=17.8mVRMS]) -45dBV -35dBV
R1=1M 0.1 V IN 1.3 V LPFB 9 V
REG
68n 10 68n BUFFER OUT 26 RECT. IN 27
FULL WAVE RECTIFIER
S1 C
AGC
10n
DELTA OUT
10k B IN 3 5 B OUT 7
+12V 27 LT001 6 3 + 4 10n 30 -12V
VO
BUFFER IN
22
24
1
AVERAGING CIRCUIT THRESHOLD
31
VCC
RF
13
VOLTAGE REGULATOR
R + LP FILTER
2k2
AGC
33
11 DOUT
AIN 14
R V REG - 0.6 V
LIN/LOG CONVERTER
12 P GND
6 GND
25 I REL
23 2 I THRESH IGAIN
All resistors in ohms, all capacitors in farads unless otherwise stated.
I REL
I THRESH
IGAIN
Fig. 7 AGC Control Stage Test Circuit
510 - 78 - 06
6
IINNIN = 63 dBV
1
30
IGAIN = 3.75 x IR RELEASE TIME (s)
20
ITHRESH = 1.875 x IR IN = - 63 dBV R1=100k
0.1
GAIN (dB)
0 0.25 0.5 0.75 1 1.25 1.5 1.75 2
10
0
0.01
-10 0 0.5 1 1.5 2 2.5 3 3.5 4
NORMALIZED I REL / I R CURRENT
NORMALIZED I
GAIN / I R CURRENT
Fig. 8 Release Time vs I REL (Fig.7 Test Circuit)
Fig. 9 AGC Gain vs IGAIN (Fig.7 Test Circuit)
-40
1
INPUT THRESHOLD (dBV)
IGAIN = 3.75 x I R CLIP LEVEL (Vp-p)
-50
RF = 50k VIN = - 30 dBV
(S3-b)
0.1
-60
-70 0 0.25 0.5 0.75 1 1.25 1.5 1.75 2 0.01 0 0.25 0.5 0.75 1 1.25 1.5 1.75 2
NORMALIZED I THRESH / I
R CURRENT
NORMALIZED I CLIP / I R CURRENT
Fig. 10 Threshold Level vs I THRESH (Fig.7 Test Circuit)
Fig. 11 Output Swing vs ICLIP (Fig.13 Test Circuit) (note 1)
0.3
I10 = 0A BIAS VOLTAGE (V)
0.25
0.2
0.15
0.1 0
0.25
0.5
0.75
1
1.25
1.5
1.75
2
NORMALIZED I BIAS / I R CURRENT
Fig. 12 Receiver Bias Voltage vs IBIAS (Fig. 14 Test Circuit)
NOTE: 1.
Switch S2 - open, S4 - closed.
7
510 - 78 - 06
CLIPPER STAGE
PARAMETER Quiescent Voltage on Pad 5 Input Bias Current (Pad 5) Quiescent Voltage on Pad 4 Quiescent Voltage on Pad 8 Output Swing High 1 (Pad 8) SYMBOL V Q5 I BIAS V Q4 V Q8 V OH1 I IN = +1A I CLIP = 0A I IN = -1A I CLIP = 0A CONDITIONS (S1 closed) RF1 =1M RF2=0 (Note 1) MIN 5 (Note 2) -5 (Note 2) (Note 3) I IN = 5A I CLIP = 1.875 x I R (Note 2) I IN = -5A I CLIP = 1.875 x I R (Note 2) (Note 3) I P8 = 10A (S2 closed) VIN = 50mVpp (S3-b) I CLIP=1.875 x IR (Note 4) 1 50 mV mV TYP 550 0 500 1.2 MAX UNITS mV nA mV V mV
Output Swing Low 1 (Pad 8)
V OL 1
Output Clip Symmetry 1 Output Swing High 2 (Pad 8)
V SYM 1 V OH 2
Output Swing Low 2 (Pad 8)
V OL 2
-
-50
-
mV
Output Clip Symmetry 2 Output Resistance (Pad 8) Clipper Voltage Gain
V SYM 2 R OUT 8 GAIN
-
1 40 12
k dB
All switches remain as shown in the Test Circuit unless otherwise stated in CONDITIONS column. NOTES: 1. IBIAS = (V7 - V7
RF = 1M
) / 1M
RF= 0
3. VSYM = (2VOH / ( VOH - VOL ))
2. V OL
= V OH = V Q8 - V8
4. GAIN = 20 log (V8 / V7)
10 K
10
b S3 S1 I 10n 10n 5 7 30 VCC
S2
VIN
IIN 1.3 V
a 68n 68n RF=10k
P8
9 13
26
27 1 31
8
VCC
2k2 3.3 ROUT VC AMP CLIPPER 11
12
6
4
All resistors in ohms, all capacitors in farads unless otherwise stated
ICLIP
Fig. 13 Clipper Test Circuit
510 - 78 - 06
8
OUTPUT STAGE
PARAMETER Quiescent Voltage on Pad 17 Min Receiver Bias Voltage Max Receiver Bias Voltage Input Resistance Pad 17 Internal Feedback Resistor Max Sinking Current (Pad 11)
NOTE: 1. V REC= V cc - V11
SYMBOL V17 VREC MIN VREC MAX RIN17 RF I SINK
CONDITIONS
MIN -
TYP 1.2 100 300 40 240 10
MAX -
UNITS V mV mV k k mA
I BIAS = 0A (Note 1) I BIAS = IR x 1.875 (Note 1) I BIAS = IR I 10 = I R (S1 closed)
-
All switches remain as shown in the Test Circuit otherwise stated in the CONDITION column.
+1.3 V
10k 68n 68n B IN 5 B OUT 7 30 31 10n 10n
I 10 D IN 10 RF S1
V CC
9 V REG 13 33
26
27
1
2k2
OUTPUT
11 D OUT
+
V BIAS
R IN 17
12 P GND
6 GND I BIAS
17
All resistors in ohms, all capacitors in farads, unless otherwise stated.
Fig. 14 Output Stage Test Circuit
COMMENTS: 1. Pin 23 and Pin 4 represent virtual ground inputs. 2. If the length of the wires between the current sources and the GP520A is extensive, it may be necessary to connect an RC filter close to the appropriate GP520A pin for noise immunity. e.g.
100k 4 ICLIP 10 GP520A
All resistors in ohms, all capacitors in farads, unless otherwise stated.
9
510 - 78 - 06
V CC C3 2n2 9 13 C1 + 33 28 50k R
VOLTAGE REGULATOR
C4 2n2 15 18 19
C6 1n5 22
C9 C5 680p 24 26 C7 68n 27
FULL WAVE RECTIFIER
C8 68n 1
AVERAGING CIRCUIT THRESHOLD
C12
68n
31 3 5
10n
50k VC 7
C11
10n
30
V cc
R
+ LP FILTER
R OUT 8
AGC
8
VC AMP CLIPPER
C2 MIC 22n
29 14
C10 10 RF 6n8
RIN14
+ PREAMP 40k
2R
+ HP FILTER -
R 10k I REF 16 25
LIN/LOG CONVERTER
OUTPUT +
LIN/LOG CONVERTER
11
LIN/LOG CONVERTER
VBIAS 23 4 17
V cc
12
6
20
21
2
All resistors in ohms, all capacitors in farads unless otherwise stated.
Fig. 15 Typical Application Circuit
V CC C3 2n2 10k 1k 28 C1 3u3 T MIC 2n2 M 2n2 10k R 1u 2n2 14 RIN14 50k 29 13 9
VOLTAGE REGULATOR
C4 2n2 15 18 19
C6 1n5 22
C5 680p 24 26
C7 68n 27
FULL WAVE RECTIFIER
C8 68n 1
AVERAGING CIRCUIT
C12
C9
50k VC 5 7
C11
10n
31
THRESHOLD
68n
3
10n
30
V cc
R
+ LP FILTER
AGC
VC AMP
8
CLIPPER
C10 10 6n8
R
+ PREAMP 40k
2R
+ HP FILTER -
R
F
OUTPUT +
LIN/LOG CONVERTER
11
LIN/LOG CONVERTER
I REF 16 25
LIN/LOG CONVERTER
VBIAS 23 4 17
12
6
20
21
2
V cc
All resistors in ohms, all capacitors in farads unless otherwise stated.
Fig. 16 Typical Telecoil Application Circuit
DOCUMENT IDENTIFICATION: DATA SHEET The product is in production. Gennum reserves the right to make changes at any time to improve reliability, function or design, in order to provide the best product possible. REVISION NOTES:
Updated to Data sheet
Gennum Corporation assumes no responsibility for the use of any circuits described herein and makes no representations that they are free from patent infringement. (c) Copyright September 1989 Gennum Corporation. All rights reserved.
Printed in Canada.
510 - 78 - 06
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